1. Technical Field
The present invention relates generally to semiconductor devices, and more particularly, to a method of reducing the gate to source/drain (hereinafter xe2x80x9cS/Dxe2x80x9d) contact spacing, thereby reducing the overall size of the device.
2. Related Art
There is an ever-present need in the semiconductor industry to reduce the size of integrated circuits, while maintaining reliability. FIG. 1 shows a related art CMOS logic device 10. The device 10 is constructed of a substrate 12, having a plurality of source/drain (S/D) regions 14 therein. A highly conductive layer 16 is located within the S/D regions 14. A gate oxide layer 17 is deposited over the surface of the substrate 12. A gate 18 is formed on the substrate 12, over the gate oxide layer 17, in areas between the S/D regions 14. Each gate 18 has a highly conductive layer 20 thereon, and a spacer 22 on each side which are approximately the same height as the gate 18. An insulative layer 28 is deposited over the spacers 22 and the gates 18. A gate contact 24, having a depth d, contacts each gate 18. A S/D contact 26, having a depth D, contacts the highly conductive layer 16 within the S/D regions 14, located between the gates 18. Because the highly conductive layers 16, 20 are at different depths (D and d, respectively), within the device 10, the height and aspect ratio of the S/D contact 26 must be considerably greater than the height and aspect ratio of the gate contacts 24.
As FIG. 1 illustrates, size reduction is limited because there is a minimum amount of gate to S/D contact spacing S required to prevent electrical connection between the gate contacts 24 and the S/D contact 26, which would produce a short within the device 10. Contributing to this limitation is what is referred to in the industry as xe2x80x9cthe canyon problem.xe2x80x9d The canyon problem arises because the highly conductive layers 16, 20 are not located at the same depth (D vs. d) within the device 10. As a result, the S/D contact hole 30 that forms the S/D contact 26 must be etched deeper than the contact hole 32 that form the gate contacts 24. Further, since it is typical for the contact holes 30, 32 to be produced having a slope of approximately 84xc2x0 to 87xc2x0 due to etching error, a minimum amount of space S between the contacts 24, 26 must be factored into the device to prevent electrical shorts.
Accordingly, there exists a need in the industry for a smaller, more compact, yet reliable semiconductor device, and a method of forming such a device.
In general, the present invention provides a reliable semiconductor device having a reduced overall size and a method of forming the same.
The first general aspect of the present invention provides a method of forming a semiconductor device, comprising the steps of: providing a substrate, having at least one shallow trench isolation therein, and a gate stack thereon; forming a gate and a dielectric isolation on the surface of the substrate; forming a non-conductive sidewall spacer on each side of the gate and dielectric isolation; forming at least one diffusion region within the substrate; removing a portion of the gate; depositing a silicide-forming layer over the surface of the logic device; depositing a conductive layer over the silicide-forming layer; planarizing the surface of the device to expose the dielectric isolations and spacers; and annealing the substrate to form a silicide layer between the conductive layer and each gate and diffusion region. This aspect allows for the production of a more compact device, having sidewall spacers, shallow trench isolations and dielectric isolations therein to protect against shorts. This aspect also provides a device having borderless contacts. In other words, contacts placed on the contact mounting surfaces of the substrate may overlap adjacent features within the device, namely, the sidewall spacers and the dielectric isolations, without producing an electrical short. This allows for the production of a device having contact mounting surfaces that can be smaller than the contacts placed thereon, as well as compensating for manufacturing errors, without producing shorts within the device. This aspect also provides sidewall spacers that extend above the contact mounting surfaces to further protect against shorts. In addition, this aspect provides a device wherein the gates and the isolations are coplanar, thereby providing substantially coplanar contact mounting surfaces, as well as providing contact mounting surfaces that are comprised of the same or similar materials. This allows for the use of contacts having uniform size and shape, thereby simplifying the manufacturing process, as well as solving the related art xe2x80x9ccanyon problemxe2x80x9d mentioned above. Further, this aspect provides a layer of silicide between the conductive layer and each of the gates and dielectric isolations, thereby enhancing the conductivity of the device.
The second general aspect of the present invention provides a semiconductor device having substantially coplanar contact mounting surfaces, comprising: a substrate having at least one diffusion region and at least one dielectric filled trench therein; at least one gate on the surface of the substrate; at least one isolation on the surface of the substrate contacting the dielectric filled trenches; a plurality of spacers bordering the gate and the isolation; and a layer of conductive material between the spacers of the gates and isolations. This aspect provides a device created by the method described in the first aspect, having similar advantages.
The third general aspect of the present invention provides a method of forming a wireless interconnection within a semiconductor device, comprising the steps of: providing a substrate including at least two logic devices, having at least one diffusion region within each logic device; and forming a region within the substrate wherein the diffusion regions of at least two logic devices are electrically connected. This aspect provides a method of providing a wireless connection within the device produced using the method of the first aspect. This aspect allows for the internal electrical connection of logic cells, without the use of external wiring.
The fourth general aspect of the present invention provides a method of forming a semiconductor device having borderless contacts, comprising the steps of: providing a substrate having at least one shallow trench isolation and at least one diffusion region therein; providing at least one isolation on a first surface of the substrate, contacting the shallow trench isolations; providing at least one gate on the first surface of the substrate, wherein the gate and the isolations are coplanar; providing sidewall spacers for each of the at least one gate and isolations; and providing a planar layer of conductive material over the substrate. This aspect provides a device created by the method described in the first aspect, having similar advantages.
A fifth general aspect of the present invention provides a semiconductor device having borderless contacts therein, comprised of: at least one shallow trench isolation and at least one diffusion region within a substrate; a dielectric isolation on a surface of the substrate contacting the shallow trench isolations having at least one discontinuity therein; at least one gate on the surface of the substrate; a plurality of sidewall spacers contacting the gates and the isolations; and a layer of conductive material between the gates and the isolations. This aspect provides a semiconductor device produced from the method described in the fourth aspect, having advantages similar to those associated with the first and fourth aspects.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention.